JOSA Workshop | Introduction to RISC-V

Chip design used to require million-dollar licenses and years of insider knowledge. RISC-V changed that. Join us in this workshop for a deep dive into the concepts of chip design and gain real hands-on experience in production-grade, hardware-accelerated security protocols implemented down to RISC-V machine code level.

What you'll learn

• High-level view of open source silicon systems
• End-to-End chip design flow
• Learn production level hardware designs operate
• Explore OpenTitan as a IP library
• FPGAs as a prototyping instrument
• Hands-on lab: Deploying PicoRV RISC-V core on FPGA

Prerequisites

Basic technical background. Computer architecture knowledge is a plus, but not required.

Registration

This workshop is free of charge, but seats are limited.

• Apply to this workshop by filling out the form below. No additional confirmation is needed.
• Priority is given to JOSA Members.

Register


Facilitator